Make the debug tests aware of multicore.

[riscv-tests.git] / debug / programs / entry.S

diff --git a/debug/programs/entry.S b/debug/programs/entry.S
index c9e319ccc0549b31d4ef148bfc2ca8c62e15556d..c3be61108e4a129b0ab2b087754d78d9d0ed1972 100755 (executable)
--- a/debug/programs/entry.S
+++ b/debug/programs/entry.S
@@ -27,7 +27,9 @@ trap_vector:
   j trap_entry
 
 handle_reset:
-  la t0, trap_entry
+  // If misa doesn't exist (or is following an old spec where it has a
+  // different number), skip the next block.
+  la t0, 3f
   csrw mtvec, t0
   csrwi mstatus, 0
 
@@ -48,6 +50,10 @@ handle_reset:
   csrwi medeleg, 0
 2:
   csrwi mie, 0
+3:
+  la t0, trap_entry
+  csrw mtvec, t0
+  csrwi mstatus, 0
 
   # initialize global pointer
 .option push
@@ -151,9 +157,16 @@ trap_entry:
   addi sp, sp, 32*REGBYTES
   mret
 
+loop_forever:
+  j loop_forever
+
   // Fill the stack with data so we can see if it was overrun.
   .align 4
 stack_bottom:
   .fill STACK_SIZE/4, 4, 0x22446688
 stack_top:
+  // Prevent stack_top from being identical to next symbol, which may cause gdb
+  // to report we're halted at stack_top which happens to be the same address
+  // as main.
+  .word 0
 #endif