Add coverage for single-core non-rtos OpenOCD.

[riscv-tests.git] / debug / targets / RISC-V / spike.cfg

diff --git a/debug/targets/RISC-V/spike.cfg b/debug/targets/RISC-V/spike.cfg
index 9b1841cb80ce01b9e736f4ae107289a889529f7f..fc20b53b4341ff600c6ef375cad8660460793df9 100644 (file)
--- a/debug/targets/RISC-V/spike.cfg
+++ b/debug/targets/RISC-V/spike.cfg
@@ -8,7 +8,7 @@ set _CHIPNAME riscv
 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
 
 gdb_report_data_abort enable