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Add coverage for single-core non-rtos OpenOCD.
[riscv-tests.git]
/
debug
/
targets
/
RISC-V
/
spike32-2.py
diff --git
a/debug/targets/RISC-V/spike32-2.py
b/debug/targets/RISC-V/spike32-2.py
index 6cf558d4b936c6634100ecde00d289990b50129c..a7b9a1c0a7a1b244afef8f4980554cbd8ec6b53c 100644
(file)
--- a/
debug/targets/RISC-V/spike32-2.py
+++ b/
debug/targets/RISC-V/spike32-2.py
@@
-5,7
+5,7
@@
import spike32 # pylint: disable=import-error
class spike32_2(targets.Target):
harts = [spike32.spike32_hart(), spike32.spike32_hart()]
- openocd_config_path = "spike.cfg"
+ openocd_config_path = "spike
-rtos
.cfg"
timeout_sec = 30
def create(self):