Allow multiple reset vectors.

[riscv-tests.git] / debug / targets / RISC-V / spike32.py

diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py
index e80f60a07a51e6ae38ee0b2afad51f201e1f0146..bcb58927bc0e55205dffa7997edbfafdf94c05f6 100644 (file)
--- a/debug/targets/RISC-V/spike32.py
+++ b/debug/targets/RISC-V/spike32.py
@@ -6,12 +6,13 @@ class spike32_hart(targets.Hart):
     ram = 0x10000000
     ram_size = 0x10000000
     instruction_hardware_breakpoint_count = 4
-    reset_vector = 0x1000
-    link_script_path = "spike64.lds"
+    reset_vectors = [0x1000]
+    link_script_path = "spike32.lds"
 
 class spike32(targets.Target):
     harts = [spike32_hart()]
     openocd_config_path = "spike.cfg"
+    timeout_sec = 30
 
     def create(self):
         return testlib.Spike(self)