Make pylint happy.

[riscv-tests.git] / debug / targets / SiFive / Freedom / U500Sim.py

diff --git a/debug/targets/SiFive/Freedom/U500Sim.py b/debug/targets/SiFive/Freedom/U500Sim.py
index 76489602bc96cedc99c1e9ce67152125736dda01..065ab08ae446b4fb76dba6b9a4968acec34b464c 100644 (file)
--- a/debug/targets/SiFive/Freedom/U500Sim.py
+++ b/debug/targets/SiFive/Freedom/U500Sim.py
@@ -1,11 +1,17 @@
-class U500Sim(Target):
+import targets
+import testlib
+
+class U500Hart(targets.Hart):
     xlen = 64
-    timeout_sec = 6000
     ram = 0x80000000
     ram_size = 256 * 1024 * 1024
     instruction_hardware_breakpoint_count = 2
-    openocd_config_path = "Freedom.cfg"
     link_script_path = "Freedom.lds"
 
+class U500Sim(targets.Target):
+    timeout_sec = 6000
+    openocd_config_path = "Freedom.cfg"
+    harts = [U500Hart()]
+
     def target(self):
         return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)