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Make the debug tests aware of multicore.
[riscv-tests.git]
/
debug
/
targets
/
SiFive
/
HiFive1.py
diff --git
a/debug/targets/SiFive/HiFive1.py
b/debug/targets/SiFive/HiFive1.py
index 813829e415116ec15a76c463924f168c14f83c87..3cb508cd0e1e358797ce7f836ffc6fdcc5046ad7 100644
(file)
--- a/
debug/targets/SiFive/HiFive1.py
+++ b/
debug/targets/SiFive/HiFive1.py
@@
-1,8
+1,11
@@
import targets
-class HiFive1
(targets.Targe
t):
+class HiFive1
Hart(targets.Har
t):
xlen = 32
ram = 0x80000000
ram_size = 16 * 1024
instruction_hardware_breakpoint_count = 2
misa = 0x40001105
+
+class HiFive1(targets.Target):
+ harts = [HiFive1Hart()]