ROM -> RAM -> ROM, waiting for debug int.

[riscv-isa-sim.git] / debug_rom / debug_rom.S

diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S
index 16890cf99464540b412d243c792482783d0629ce..577edbb50c266a596ed6443889b68faac90b9182 100755 (executable)
--- a/debug_rom/debug_rom.S
+++ b/debug_rom/debug_rom.S
@@ -36,7 +36,7 @@ clear_debint:
 clear_debint_loop:
         csrr    s1, DCSR
         andi    s1, s1, (1<<DCSR_DEBUGINT_OFFSET)
-        bnez    s1, wait_for_interrupt
+        bnez    s1, clear_debint_loop
 
         # Restore s1.
         csrr    s1, MCPUID