Refactor how we track in-progress operations.

[riscv-isa-sim.git] / debug_rom / debug_rom.S

diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S
index ca58ee475473dd53043e074ab3e253c7c63cb2f7..9825d4864455cacfeb6ed8166a414f6ca991d03d 100755 (executable)
--- a/debug_rom/debug_rom.S
+++ b/debug_rom/debug_rom.S
@@ -32,6 +32,7 @@ resume:
 clear_debint:
         csrr    s1, CSR_MHARTID
         sw      s1, CLEARDEBINT(zero)
+        # TODO: race: what if the debugger sets debug int at this point?
 clear_debint_loop:
         csrr    s1, DCSR
         andi    s1, s1, (1<<DCSR_DEBUGINT_OFFSET)