Fix race using fence.

[riscv-isa-sim.git] / debug_rom / debug_rom.S

diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S
index 9825d4864455cacfeb6ed8166a414f6ca991d03d..a3339b45ed1f915fbdf83cd8e5f3b99349d55e38 100755 (executable)
--- a/debug_rom/debug_rom.S
+++ b/debug_rom/debug_rom.S
@@ -32,11 +32,7 @@ resume:
 clear_debint:
         csrr    s1, CSR_MHARTID
         sw      s1, CLEARDEBINT(zero)
-        # TODO: race: what if the debugger sets debug int at this point?
-clear_debint_loop:
-        csrr    s1, DCSR
-        andi    s1, s1, (1<<DCSR_DEBUGINT_OFFSET)
-        bnez    s1, clear_debint_loop
+        fence
 
         # Restore s1.
         csrr    s1, CSR_MISA