ls180Conf.chipConf.ioPadGauge = 'niolib'
ls180Conf.coreSize = (l(coreSize ), l(coreSize ))
ls180Conf.chipSize = (l(coreSize+3360), l(coreSize+3360))
+ # ooo, how annoying. nsxlib (only 6 METAL) cannot cope with 3 clocks!
#ls180Conf.useHTree('core.por_clk') # output from the PLL, needs to be H-Tree
- #ls180Conf.useHTree('test_issuer.pllclk_clk') # output from the PLL, needs to be H-Tree
ls180Conf.useHTree('jtag_tck_from_pad')
ls180Conf.useHTree('sys_clk_from_pad')