Ignore merging past ffs that we are not properly merging

[yosys.git] / frontends / verific / verific.cc

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 284d5db31f6374648426acb6a44e61e672881873..d19d837ffcca33316b8271ffb1d664c32ad06f36 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -987,6 +987,7 @@ void VerificImporter::merge_past_ffs(pool<RTLIL::Cell*> &candidates)
 
        for (auto cell : candidates)
        {
+               if (cell->type != ID($dff)) continue;
                SigBit clock = cell->getPort(ID::CLK);
                bool clock_pol = cell->getParam(ID::CLK_POLARITY).as_bool();
                database[make_pair(clock, int(clock_pol))].insert(cell);