Improve ma_fetch test to cover JAL and branches

[riscv-tests.git] / isa / rv64si / ma_fetch.S

diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S
index 544daa0140a2703b6754ad7b14cc73b22f1d734c..d4e5b44c4521438fcd388ef76ee11131059f7ab2 100644 (file)
--- a/isa/rv64si/ma_fetch.S
+++ b/isa/rv64si/ma_fetch.S
@@ -32,9 +32,10 @@ RVTEST_CODE_BEGIN
   jalr t1, t0, 2
 1:
   .option rvc
-  c.j fail
+  c.j 1f
   c.j 2f
   .option norvc
+1:
   j fail
 2:
 
@@ -53,9 +54,53 @@ RVTEST_CODE_BEGIN
   jalr t1, t0, 3
 1:
   .option rvc
-  c.j fail
+  c.j 1f
   c.j 2f
   .option norvc
+1:
+  j fail
+2:
+
+  # Like test 2, but with jal instead of jalr.
+  li TESTNUM, 5
+  li t1, 0
+  la t0, 1f
+  jal t1, 2f
+1:
+  .option rvc
+  c.j 1f
+2:
+  c.j 2f
+  .option norvc
+1:
+  j fail
+2:
+
+  # Like test 2, but with a taken branch instead of jalr.
+  li TESTNUM, 6
+  li t1, 0
+  la t0, 1f
+  beqz x0, 2f
+1:
+  .option rvc
+  c.j 1f
+2:
+  c.j 2f
+  .option norvc
+1:
+  j fail
+2:
+
+  # Not-taken branches should not trap, even without RVC.
+  li TESTNUM, 7
+  bnez x0, 1f
+  j 2f
+  .option rvc
+  c.j 1f
+1:
+  c.j 1f
+  .option norvc
+1:
   j fail
 2:
 
@@ -65,11 +110,15 @@ RVTEST_CODE_BEGIN
 
   .align 2
 stvec_handler:
-  # tests 2 and 4 should trap
+  # tests 2, 4, 5, and 6 should trap
   li a0, 2
   beq TESTNUM, a0, 1f
   li a0, 4
   beq TESTNUM, a0, 1f
+  li a0, 5
+  beq TESTNUM, a0, 1f
+  li a0, 6
+  beq TESTNUM, a0, 1f
   j fail
 1: