Rv32ud tests (#108)

[riscv-tests.git] / isa / rv64ud / fcmp.S

diff --git a/isa/rv64ud/fcmp.S b/isa/rv64ud/fcmp.S
index 173dc88d80afff405fd10e6bdc5cf5566937ebe9..7727a2871fc5af012f2ba1b957269af117b3d1bf 100644 (file)
--- a/isa/rv64ud/fcmp.S
+++ b/isa/rv64ud/fcmp.S
@@ -17,13 +17,32 @@ RVTEST_CODE_BEGIN
   # Arithmetic tests
   #-------------------------------------------------------------
 
-  TEST_FP_CMP_OP_D( 2, feq.d, 1, -1.36, -1.36)
-  TEST_FP_CMP_OP_D( 3, fle.d, 1, -1.36, -1.36)
-  TEST_FP_CMP_OP_D( 4, flt.d, 0, -1.36, -1.36)
-
-  TEST_FP_CMP_OP_D( 5, feq.d, 0, -1.37, -1.36)
-  TEST_FP_CMP_OP_D( 6, fle.d, 1, -1.37, -1.36)
-  TEST_FP_CMP_OP_D( 7, flt.d, 1, -1.37, -1.36)
+#if __riscv_xlen == 32
+    # Replace the function with the 32-bit variant defined in test_macros.h
+    #undef TEST_FP_CMP_OP_D
+    #define TEST_FP_CMP_OP_D TEST_FP_CMP_OP_D32
+#endif
+
+  TEST_FP_CMP_OP_D( 2, feq.d, 0x00, 1, -1.36, -1.36)
+  TEST_FP_CMP_OP_D( 3, fle.d, 0x00, 1, -1.36, -1.36)
+  TEST_FP_CMP_OP_D( 4, flt.d, 0x00, 0, -1.36, -1.36)
+
+  TEST_FP_CMP_OP_D( 5, feq.d, 0x00, 0, -1.37, -1.36)
+  TEST_FP_CMP_OP_D( 6, fle.d, 0x00, 1, -1.37, -1.36)
+  TEST_FP_CMP_OP_D( 7, flt.d, 0x00, 1, -1.37, -1.36)
+
+  # Only sNaN should signal invalid for feq.
+  TEST_FP_CMP_OP_D( 8, feq.d, 0x00, 0, NaN, 0)
+  TEST_FP_CMP_OP_D( 9, feq.d, 0x00, 0, NaN, NaN)
+  TEST_FP_CMP_OP_D(10, feq.d, 0x10, 0, sNaN, 0)
+
+  # qNaN should signal invalid for fle/flt.
+  TEST_FP_CMP_OP_D(11, flt.d, 0x10, 0, NaN, 0)
+  TEST_FP_CMP_OP_D(12, flt.d, 0x10, 0, NaN, NaN)
+  TEST_FP_CMP_OP_D(13, flt.d, 0x10, 0, sNaN, 0)
+  TEST_FP_CMP_OP_D(14, fle.d, 0x10, 0, NaN, 0)
+  TEST_FP_CMP_OP_D(15, fle.d, 0x10, 0, NaN, NaN)
+  TEST_FP_CMP_OP_D(16, fle.d, 0x10, 0, sNaN, 0)
 
   TEST_PASSFAIL