from nmigen_soc import wishbone
from nmigen_soc.memory import MemoryMap
+from nmigen_soc.periph import ConstantMap
from . import Peripheral
def init(self, init):
self._mem.init = init
+ @property
+ def constant_map(self):
+ return ConstantMap(
+ SIZE = self.size,
+ )
+
def elaborate(self, platform):
m = Module()