#
# Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+#
# Based on code from Kermarrec, Licensed BSD-2-Clause
#
# Modifications for the Libre-SOC Project funded by NLnet and NGI POINTER
from nmigen import (Record, Module, Signal, Elaboratable)
from nmigen.compat.sim import run_simulation
-from lambdasoc.periph.hyperram import HyperRAM
+from lambdasoc.periph.hyperram import HyperRAM, HyperRAMPads, TestHyperRAMPHY
def c2bool(c):
return {"-": 1, "_": 0}[c]
return (yield bus.dat_r)
-class Pads: pass
-
-
-class HyperRamPads:
- def __init__(self, dw=8):
- self.clk = Signal()
- self.cs_n = Signal()
- self.dq = Record([("oe", 1), ("o", dw), ("i", dw)])
- self.rwds = Record([("oe", 1), ("o", dw//8), ("i", dw//8)])
-
-
-class TestHyperRAMPHY(Elaboratable):
- def __init__(self, pads):
- self.pads = pads
- self.clk = pads.clk
- self.cs = Signal()
- self.dq_o = pads.dq.o
- self.dq_i = pads.dq.i
- self.dq_oe = pads.dq.oe
- self.rwds_o = pads.rwds.o
- self.rwds_oe = Signal()
-
- def elaborate(self, platform):
- m = Module()
- m.d.comb += self.pads.cs_n.eq(~self.cs)
- m.d.comb += self.pads.rwds.oe.eq(self.rwds_oe)
- return m
-
-
class TestHyperBusWrite(unittest.TestCase):
def test_hyperram_write(self):
(yield dut.phy.pads.rwds.o))
yield
- dut = HyperRAM(io=HyperRamPads(), phy_kls=TestHyperRAMPHY)
+ dut = HyperRAM(io=HyperRAMPads(), phy_kls=TestHyperRAMPHY)
run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)],
vcd_name="sim.vcd")
(yield dut.phy.pads.rwds.oe))
yield
- dut = HyperRAM(io=HyperRamPads(), phy_kls=TestHyperRAMPHY)
+ dut = HyperRAM(io=HyperRAMPads(), phy_kls=TestHyperRAMPHY)
run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)],
vcd_name="rd_sim.vcd")
(yield dut.phy.pads.rwds.oe))
yield
- dut = HyperRAM(io=HyperRamPads(), phy_kls=TestHyperRAMPHY)
+ dut = HyperRAM(io=HyperRAMPads(), phy_kls=TestHyperRAMPHY)
run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)],
vcd_name="rd_sim.vcd")