rename PLL pins to match LIP6.fr PLL

[libresoc-litex.git] / libresoc / ls180.py

diff --git a/libresoc/ls180.py b/libresoc/ls180.py
index ab8fb33e7926136a10d684fb729f91f114bf3936..a03eef9a9408be3d876fa135b2dcebded0e5b41d 100644 (file)
--- a/libresoc/ls180.py
+++ b/libresoc/ls180.py
@@ -57,8 +57,8 @@ def io():
         ("sys_clk", 0, Pins("G2"), IOStandard("LVCMOS33")),
         ("sys_rst",   0, Pins("R1"), IOStandard("LVCMOS33")),
         ("sys_clksel_i",   0, Pins("R1 R2"), IOStandard("LVCMOS33")),
-        ("sys_pll_18_o",   0, Pins("R1"), IOStandard("LVCMOS33")),
-        ("sys_pll_lck_o",   0, Pins("R1"), IOStandard("LVCMOS33")),
+        ("sys_pll_testout_o",   0, Pins("R1"), IOStandard("LVCMOS33")),
+        ("sys_pll_vco_o",   0, Pins("R1"), IOStandard("LVCMOS33")),
 
         # JTAG0: 4 pins
         ("jtag", 0,