soc/integration: add bus standard parser arguments

[litex.git] / litex / soc / interconnect / axi.py

diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py
index 6d00ca640a3a461003d027f6e6e63d0e790ed12f..646f36e3981649a978f6bd9a92ade676e512cc69 100644 (file)
--- a/litex/soc/interconnect/axi.py
+++ b/litex/soc/interconnect/axi.py
@@ -1043,7 +1043,8 @@ class AXILiteDecoder(Module):
     {slaves}
     """.format(slaves=_doc_slaves)
 
-    def __init__(self, master, slaves):
+    def __init__(self, master, slaves, register=False):
+        # TODO: unused register argument
         addr_shift = log2_int(master.data_width//8)
 
         channels = {
@@ -1124,7 +1125,7 @@ class AXILiteInterconnectShared(Module):
     {slaves}
     """.format(slaves=AXILiteDecoder._doc_slaves)
 
-    def __init__(self, masters, slaves, timeout_cycles=1e6):
+    def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
         # TODO: data width
         shared = AXILiteInterface()
         self.submodules.arbiter = AXILiteArbiter(masters, shared)
@@ -1140,7 +1141,7 @@ class AXILiteCrossbar(Module):
     {slaves}
     """.format(slaves=AXILiteDecoder._doc_slaves)
 
-    def __init__(self, masters, slaves, timeout_cycles=1e6):
+    def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
         matches, busses = zip(*slaves)
         access_m_s = [[AXILiteInterface() for j in slaves] for i in masters]  # a[master][slave]
         access_s_m = list(zip(*access_m_s))  # a[slave][master]