build/sim: allow for arbitrary clocks generation using clockers

[litex.git] / litex / tools / litex_sim.py

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 24c8b91444edf6e4253e6e2e7fd6d26d4d66a8d6..c07cb3a98f0679dc2b7d07714465165d94956f84 100755 (executable)
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -343,9 +343,9 @@ def main():
     soc_kwargs     = soc_sdram_argdict(args)
     builder_kwargs = builder_argdict(args)
 
-    # timebase is half of the period of main simulation clock
     sys_clk_freq = int(1e6)
-    sim_config = SimConfig(default_clk="sys_clk", timebase_ps=(1/sys_clk_freq / 2) * 1e12)
+    sim_config = SimConfig()
+    sim_config.add_clocker("sys_clk", freq_hz=sys_clk_freq)
 
     # Configuration --------------------------------------------------------------------------------