core: Allow multiple loadstore instructions to be in flight

[microwatt.git] / loadstore1.vhdl

diff --git a/loadstore1.vhdl b/loadstore1.vhdl
index 66700e88cabc0c7f3fc3c8eb09b2c1cb5e72838b..ee4507b15a30736bf84645978f78bad39dff1ddd 100644 (file)
--- a/loadstore1.vhdl
+++ b/loadstore1.vhdl
@@ -155,6 +155,7 @@ architecture behave of loadstore1 is
 
     signal busy     : std_ulogic;
     signal complete : std_ulogic;
+    signal in_progress : std_ulogic;
     signal flushing : std_ulogic;
 
     signal store_sp_data : std_ulogic_vector(31 downto 0);
@@ -494,13 +495,13 @@ begin
         req_in <= v;
     end process;
 
-    --busy <= r1.req.valid and ((r1.req.dc_req and not r1.issued) or
-    --                          (r1.issued and d_in.error) or
-    --                          stage2_busy_next or
-    --                          (r1.req.dc_req and r1.req.two_dwords and not r1.req.dword_index));
+    busy <= r1.req.valid and ((r1.req.dc_req and not r1.issued) or
+                              (r1.issued and d_in.error) or
+                              stage2_busy_next or
+                              (r1.req.dc_req and r1.req.two_dwords and not r1.req.dword_index));
     complete <= r2.one_cycle or (r2.wait_dc and d_in.valid) or
                 (r2.wait_mmu and m_in.done) or r3.convert_lfs;
-    busy <= r1.req.valid or (r2.req.valid and not complete);
+    in_progress <= r1.req.valid or (r2.req.valid and not complete);
 
     stage1_issue_enable <= r3.stage1_en and not (r1.req.valid and r1.req.mmu_op) and
                            not (r2.req.valid and r2.req.mmu_op);
@@ -940,6 +941,7 @@ begin
 
         -- update busy signal back to execute1
         e_out.busy <= busy;
+        e_out.in_progress <= in_progress;
 
         -- Busy calculation.
         stage3_busy_next <= r2.req.valid and not (complete or part_done or exception);