use git submodule soclayout for source files, rather than

[soc-cocotb-sim.git] / ls180 / experiment9_recon / run_iverilog_ls180.sh

diff --git a/ls180/experiment9_recon/run_iverilog_ls180.sh b/ls180/experiment9_recon/run_iverilog_ls180.sh
index eae098658c633a07ef7fc4a433c17267c49953df..9dba6e64ec0d02913989c66873dc1541161cb0a3 100755 (executable)
--- a/ls180/experiment9_recon/run_iverilog_ls180.sh
+++ b/ls180/experiment9_recon/run_iverilog_ls180.sh
@@ -1,5 +1,11 @@
 #!/bin/sh
 
+SRCDIR=../../soclayout/experiments9/non_generated/
+cp $SRCDIR/full_core_4_4ksram_litex_ls180_recon.v litex_ls180.v
+cp $SRCDIR/full_core_4_4ksram_libresoc_recon.v libresoc.v
+cp $SRCDIR/pll.v .
+cp $SRCDIR/ls180.v .
+
 touch mem.init mem_1.init mem_2.init mem_3.init mem_4.init
 # Only run test in reset state as running CPU takes too much time to simulate
 make \