Fix pre-layout simulation with 4K SRAM blocks.

[soc-cocotb-sim.git] / ls180 / pre_pnr / Makefile

diff --git a/ls180/pre_pnr/Makefile b/ls180/pre_pnr/Makefile
index 4fbc60f119e0df5a3bff4b559bc82469c4c3962f..6a60bb45b0e76d11e73bc6d73a8cac17012c0d28 100644 (file)
--- a/ls180/pre_pnr/Makefile
+++ b/ls180/pre_pnr/Makefile
@@ -7,6 +7,7 @@ TOPLEVEL_LANG := verilog
 # within soc repo, as submodule, this works after "make ls180"
 # is run inside the litex/florent subdirectory
 VERILOG_SOURCES := \
+  ../SPBlock_512W64B8W.v \
   ../../../litex/florent/libresoc.v \
   ../../../litex/florent/ls180.v \
 # END VERILOG_SOURCES