add first cut at wishbone jtag unit test

[soc-cocotb-sim.git] / ls180 / pre_pnr / README.md

diff --git a/ls180/pre_pnr/README.md b/ls180/pre_pnr/README.md
index 0f06209536d1dae3eb17a3b48c2161e6fd7cd8fb..142f8955e789851c17fb83ecaf50b0793c88947c 100644 (file)
--- a/ls180/pre_pnr/README.md
+++ b/ls180/pre_pnr/README.md
@@ -9,6 +9,9 @@ simulators, run scripts are provided that call the Makefile:
 # Dependency
 
 * cocotb: `pip install cocotb`
+* cocotb-bus: git clone https://github.com/cocotb/cocotb-bus/
+  then "python3 setup.py develop"
+* cocotbext
 * c4m-jtag: install according to HDL workflow
 * iverilog: `apt install iverilog`
 * `../libresoc.v`, `../ls180.v`: run `make ls180_verilog` in soc directory,