update README

[libresoc-litex.git] / ls180soc.py

diff --git a/ls180soc.py b/ls180soc.py
index acf2e58714ea9fe4b43e016b9af9b99ea3908851..d3e0dd9d365d90d35262fb82899fbc6e451bd276 100755 (executable)
--- a/ls180soc.py
+++ b/ls180soc.py
@@ -6,7 +6,8 @@ from functools import reduce
 from operator import or_
 
 from migen import (Signal, FSM, If, Display, Finish, NextValue, NextState,
-                   Cat, Record, ClockSignal, wrap, ResetInserter)
+                   Cat, Record, ClockSignal, wrap, ResetInserter,
+                   ClockDomain, ResetSignal)
 
 from litex.build.generic_platform import Pins, Subsignal
 from litex.build.sim import SimPlatform
@@ -25,6 +26,7 @@ from litedram.phy.model import SDRAMPHYModel
 from litedram.common import PHYPadsCombiner, PhySettings
 from litedram.phy.dfi import Interface as DFIInterface
 from litex.soc.cores.spi import SPIMaster
+from litex.soc.cores.bitbang import SPIMaster as SPIMasterBitbang
 from litex.soc.cores.pwm import PWM
 #from litex.soc.cores.bitbang import I2CMaster
 from litex.soc.cores import uart
@@ -421,18 +423,29 @@ class LibreSoCSim(SoCCore):
                 self.bus.add_slave(name=name, slave=sram_wb, region=ics_region)
 
         # CRG -----------------------------------------------------------------
-        self.submodules.crg = CRG(platform.request("sys_clk"),
+        # power-on-reset still based on PLL, leave sys_rst HI until
+        # PLL stabilises
+        pll_clk = self.cpu.pllclk_o # PLL into cpu
+        self.submodules.crg = CRG(pll_clk,
                                   platform.request("sys_rst"))
 
         if hasattr(self.cpu, "clk_sel"):
             # PLL/Clock Select
             clksel_i = platform.request("sys_clksel_i")
-            pll18_o = platform.request("sys_pll_18_o")
-            pll_lck_o = platform.request("sys_pll_lck_o")
+            pll_test_o = platform.request("sys_pll_testout_o")
+            pll_vco_o = platform.request("sys_pll_vco_o")
 
             self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select
-            self.comb += pll18_o.eq(self.cpu.pll_18_o) # "test feed" from PLL
-            self.comb += pll_lck_o.eq(self.cpu.pll_lck_o) # PLL lock flag
+            self.comb += pll_test_o.eq(self.cpu.pll_test_o) # "test" from PLL
+            self.comb += pll_vco_o.eq(self.cpu.pll_vco_o) # PLL lock flag
+            cd_cpu = ClockDomain()
+            cd_pll = ClockDomain("pll", reset_less=True)
+            self.clock_domains.cd_pll = cd_pll
+            sys_clk = platform.request("sys_pllclk") # incoming clock
+            self.comb += self.cpu.pll_24_i.eq(sys_clk)
+            self.comb += self.cd_pll.clk.eq(self.cpu.pllclk_o) # PLL into cpu
+            #self.comb += self.cd_cpu.rst.eq(ResetSignal())
+            #self.comb += self.cpu.cpu_clk.eq(cd_cpu.clk)
 
         #ram_init = []
 
@@ -505,19 +518,22 @@ class LibreSoCSim(SoCCore):
 
         # SPI Master
         print ("cpupadkeys", self.cpu.cpupads.keys())
-        if hasattr(self.cpu.cpupads, 'mspi0'):
-            sd_clk_freq = 8e6
+        if 'mspi0' in self.cpu.cpupads:
             pads = self.cpu.cpupads['mspi0']
-            spimaster = SPIMaster(pads, 8, self.sys_clk_freq, sd_clk_freq)
-            spimaster.add_clk_divider()
+            if False: # XXX needs to be greater than 1-bit wide, use bitbang
+                sd_clk_freq = 8e6
+                spimaster = SPIMaster(pads, 4, self.sys_clk_freq, sd_clk_freq)
+                spimaster.add_clk_divider()
+            else:
+                spimaster = SPIMasterBitbang(pads)
             setattr(self.submodules, 'spimaster', spimaster)
             self.add_csr('spimaster')
 
-        if hasattr(self.cpu.cpupads, 'mspi1'):
+        if 'mspi1' in self.cpu.cpupads:
             # SPI SDCard (1 wide)
             spi_clk_freq = 400e3
             pads = self.cpu.cpupads['mspi1']
-            spisdcard = SPIMaster(pads, 8, self.sys_clk_freq, spi_clk_freq)
+            spisdcard = SPIMaster(pads, 2, self.sys_clk_freq, spi_clk_freq)
             spisdcard.add_clk_divider()
             setattr(self.submodules, 'spisdcard', spisdcard)
             self.add_csr('spisdcard')