Package c4m-jtag

[soc.git] / nix / verilog.nix

diff --git a/nix/verilog.nix b/nix/verilog.nix
index cb6df044788efbae3c918bc48dc74eb1bd18b648..afd884bf6ee16c71c47856893e17211269fc48fb 100644 (file)
--- a/nix/verilog.nix
+++ b/nix/verilog.nix
@@ -10,7 +10,9 @@ stdenv.mkDerivation {
 
   strictDeps = true;
 
-  nativeBuildInputs = with python3Packages; [ nmigen-soc python libresoc-ieee754fpu libresoc-openpower-isa ];
+  nativeBuildInputs = with python3Packages; [
+    c4m-jtag nmigen-soc python libresoc-ieee754fpu libresoc-openpower-isa
+  ];
 
   configurePhase = "true";