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[libreriscv.git] / nlnet_2023_simplev_riscv.mdwn

diff --git a/nlnet_2023_simplev_riscv.mdwn b/nlnet_2023_simplev_riscv.mdwn
index 96d55a7e49835a516ad5a1b66a63ec461f386460..208fe42e4e96b546ebf6bcaba9adb647369462af 100644 (file)
--- a/nlnet_2023_simplev_riscv.mdwn
+++ b/nlnet_2023_simplev_riscv.mdwn
@@ -1,7 +1,7 @@
 # NLnet Simple-V ISA Expansion Project Grant
 
-* Code:        2023-12-XXX
-* Submitted: XX Dec 2023
+* Code:        2023-12-059
+* Submitted: 24 Nov 2023
 * Toplevel bugreport: <https://bugs.libre-soc.org/show_bug.cgi?id=1211>
 
 This project is applying for funding through the [NGI Zero Core Fund](https://nlnet.nl/core), a fund established by [NLnet](https://nlnet.nl) with financial support from the European Commission's [Next Generation Internet](https://ngi.eu) programme under grant agreement No 101092990.
@@ -87,7 +87,7 @@ for this development programme over the past five years, and for the project in
 Other modern ISAs claiming to be Vectors are in fact Packed or Predicated SIMD.
 True Cray-style Vector ISAs do not have Vertical-First or Data-Dependent
 Fail-First because these are entirely novel Computer Science concepts
-(developnet of which entirely funded by NLnet, with gratitude).
+(development of which entirely funded by NLnet, with gratitude).
 Bottom line there are zero comparable projects but the project has learned
 significantly from past ISAs dating back as far as the early 1960s.
 
@@ -96,7 +96,7 @@ significantly from past ISAs dating back as far as the early 1960s.
 The key technical challenge in this project is to rework the special Simple-V
 instructions (from the early iteration of four years ago) that enable efficiency and performance from RISC-V that would normally only be obtained from high performance architectures like POWER. The newly developed instructions will be comprehensively tested and verified, both theoretically and practically in a simulator that leads the way to its use in the widespread developer community. 
 
-Based on the previous work of Vectorising RISC-V and POWER using Simple-V already, this project is well within the scope of the experienced teams at LibreSOC and RED Semiconductor, but is extremely detailed and comprehensive, requiring meticulous attention to detail and a very high standard of Project Management. This is a sustained standard and practices developed already over a five year period that will continue to be rigorously applied.
+Based on the previous work of Vectorising RISC-V and POWER using Simple-V already, this project is well within the scope of the experienced LibreSOC team, but is extremely detailed and comprehensive, requiring meticulous attention to detail and a very high standard of Project Management. This is a sustained standard and practices developed already over a five year period that will continue to be rigorously applied.
 
 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?