back.pysim: implement sim.add_clock(if_exists=True).

[nmigen.git] / nmigen / back / pysim.py

diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py
index 8471b51806ded606ac4a68a774a6be22fba6528f..3c73eaee9ebcc4e3ee629f5e5ed5917b9908f6a7 100644 (file)
--- a/nmigen/back/pysim.py
+++ b/nmigen/back/pysim.py
@@ -438,7 +438,7 @@ class Simulator:
         sync_process = sync_process()
         self.add_process(sync_process)
 
-    def add_clock(self, period, phase=None, domain="sync"):
+    def add_clock(self, period, *, phase=None, domain="sync", if_exists=False):
         if self._fastest_clock == self._epsilon or period < self._fastest_clock:
             self._fastest_clock = period
         if domain in self._all_clocks:
@@ -453,8 +453,11 @@ class Simulator:
                 clk = domain_obj.clk
                 break
         else:
-            raise ValueError("Domain '{}' is not present in simulation"
-                             .format(domain))
+            if if_exists:
+                return
+            else:
+                raise ValueError("Domain '{}' is not present in simulation"
+                                 .format(domain))
         def clk_process():
             yield Passive()
             yield Delay(phase)