lib.fifo.AsyncFIFOBuffered: fix output register accounting

[nmigen.git] / nmigen / lib / fifo.py

diff --git a/nmigen/lib/fifo.py b/nmigen/lib/fifo.py
index ceb254d19d7f3f50af76731e1876975f8dbee2bc..0cab22587ad5a700a4e8c1b4d211dee4ac6c5729 100644 (file)
--- a/nmigen/lib/fifo.py
+++ b/nmigen/lib/fifo.py
@@ -509,7 +509,7 @@ class AsyncFIFOBuffered(Elaboratable, FIFOInterface):
         ]
 
         r_consume_buffered = Signal()
-        m.d.comb += r_consume_buffered.eq(self.r_rdy - self.r_en)
+        m.d.comb += r_consume_buffered.eq((self.r_rdy - self.r_en) & self.r_rdy)
         m.d[self._r_domain] += self.r_level.eq(fifo.r_level + r_consume_buffered)
 
         w_consume_buffered = Signal()