""",
"{{name}}.ys": r"""
# {{autogenerated}}
- {% for file in platform.iter_extra_files(".v") -%}
+ {% for file in platform.iter_files(".v") -%}
read_verilog {{get_override("read_verilog_opts")|options}} {{file}}
{% endfor %}
- {% for file in platform.iter_extra_files(".sv") -%}
+ {% for file in platform.iter_files(".sv") -%}
read_verilog -sv {{get_override("read_verilog_opts")|options}} {{file}}
{% endfor %}
- {% for file in platform.iter_extra_files(".il") -%}
+ {% for file in platform.iter_files(".il") -%}
read_ilang {{file}}
{% endfor %}
read_ilang {{name}}.il
-dev {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}} \
-lpf {{name}}.lpf \
-synthesis synplify
- {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
+ {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%}
prj_src add {{file|tcl_escape}}
{% endfor %}
prj_src add {{name}}.v