lib.cdc: in AsyncFFSynchronizer(), rename domain= to o_domain=.
[nmigen.git] / nmigen / vendor / xilinx_7series.py
index 800b5286e0d59113a522a8ca6a9a6678f6d0edb3..5c35469dff8ce377f214bd3ab24e12bc5335bbff 100644 (file)
@@ -613,7 +613,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
             m.d.comb += ResetSignal("async_ff").eq(~async_ff_sync.i)
 
         m.d.comb += [
-            ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._domain)),
+            ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._o_domain)),
             async_ff_sync.o.eq(flops[-1])
         ]