lib.cdc: in AsyncFFSynchronizer(), rename domain= to o_domain=.
[nmigen.git] / nmigen / vendor / xilinx_ultrascale.py
index 3a74d54e37298f5b8f642e2bea4eb1ec05619577..937b346fa8b67d1bda697e5c1a41deb19a27bc8a 100644 (file)
@@ -429,7 +429,7 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
             m.d.comb += ResetSignal("async_ff").eq(~async_ff_sync.i)
 
         m.d.comb += [
-            ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._domain)),
+            ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._o_domain)),
             async_ff_sync.o.eq(flops[-1])
         ]