wishbone.bus: add Interface.

[nmigen-soc.git] / nmigen_soc / csr / bus.py

diff --git a/nmigen_soc/csr/bus.py b/nmigen_soc/csr/bus.py
index a8376a754dd8dbdef073efcd64e28fcb8b0a31f2..3e3e992d920223137896d13f87b106cc79098982 100644 (file)
--- a/nmigen_soc/csr/bus.py
+++ b/nmigen_soc/csr/bus.py
@@ -105,7 +105,7 @@ class Interface(Record):
     data_width : int
         Data width. Registers are accessed in ``data_width`` sized chunks.
     alignment : int
-        Alignment. See :class:`MemoryMap`.
+        Register and window alignment. See :class:`MemoryMap`.
     name : str
         Name of the underlying record.