wishbone.bus.Interface: add support for LOCK_IO signal.

[nmigen-soc.git] / nmigen_soc / test / test_wishbone_bus.py

diff --git a/nmigen_soc/test/test_wishbone_bus.py b/nmigen_soc/test/test_wishbone_bus.py
index 00da53012c51bb942962df4a358be76f297374b3..4380d21b1dba9d5f0099628c1d5b75daa2aaea5f 100644 (file)
--- a/nmigen_soc/test/test_wishbone_bus.py
+++ b/nmigen_soc/test/test_wishbone_bus.py
@@ -44,7 +44,7 @@ class InterfaceTestCase(unittest.TestCase):
 
     def test_optional(self):
         iface = Interface(addr_width=32, data_width=32,
-                          optional={"rty", "err", "stall", "cti", "bte"})
+                          optional={"rty", "err", "stall", "lock", "cti", "bte"})
         self.assertEqual(iface.layout, Layout.cast([
             ("adr",   32, DIR_FANOUT),
             ("dat_w", 32, DIR_FANOUT),
@@ -57,6 +57,7 @@ class InterfaceTestCase(unittest.TestCase):
             ("err",   1,  DIR_FANIN),
             ("rty",   1,  DIR_FANIN),
             ("stall", 1,  DIR_FANIN),
+            ("lock",  1,  DIR_FANOUT),
             ("cti",   CycleType,    DIR_FANOUT),
             ("bte",   BurstTypeExt, DIR_FANOUT),
         ]))