wishbone: optimise SRAM addr_width

[nmigen-soc.git] / nmigen_soc / wishbone / sram.py

diff --git a/nmigen_soc/wishbone/sram.py b/nmigen_soc/wishbone/sram.py
index 3ee165ec4bad7a4603d48985773c8a7a6c5e2641..b72687dd544a80f7b4dcb5149ed930b5b000a7e4 100644 (file)
--- a/nmigen_soc/wishbone/sram.py
+++ b/nmigen_soc/wishbone/sram.py
@@ -25,7 +25,7 @@ class SRAM(Elaboratable):
         if not read_only:
             self._memdepth += self.memory.depth
         if bus is None:
-            bus = Interface(addr_width=bits_for(self._memdepth),
+            bus = Interface(addr_width=max(0, log2_int(self._memdepth, need_pow2=False)),
                             data_width=self.memory.width,
                             granularity=granularity,
                             features=features,