+// See LICENSE for license details.
+
#ifndef _RISCV_CACHE_SIM_H
#define _RISCV_CACHE_SIM_H
#include <cstring>
#include <string>
#include <map>
-#include <stdint.h>
+#include <cstdint>
class lfsr_t
{
public:
cache_sim_t(size_t sets, size_t ways, size_t linesz, const char* name);
cache_sim_t(const cache_sim_t& rhs);
- ~cache_sim_t();
+ virtual ~cache_sim_t();
void access(uint64_t addr, size_t bytes, bool store);
void print_stats();
{
public:
icache_sim_t(const char* config) : cache_memtracer_t(config, "I$") {}
- bool interested_in_range(uint64_t begin, uint64_t end, bool store, bool fetch)
+ bool interested_in_range(uint64_t begin, uint64_t end, access_type type)
{
- return fetch;
+ return type == FETCH;
}
- void trace(uint64_t addr, size_t bytes, bool store, bool fetch)
+ void trace(uint64_t addr, size_t bytes, access_type type)
{
- if (fetch) cache->access(addr, bytes, false);
+ if (type == FETCH) cache->access(addr, bytes, false);
}
};
{
public:
dcache_sim_t(const char* config) : cache_memtracer_t(config, "D$") {}
- bool interested_in_range(uint64_t begin, uint64_t end, bool store, bool fetch)
+ bool interested_in_range(uint64_t begin, uint64_t end, access_type type)
{
- return !fetch;
+ return type == LOAD || type == STORE;
}
- void trace(uint64_t addr, size_t bytes, bool store, bool fetch)
+ void trace(uint64_t addr, size_t bytes, access_type type)
{
- if (!fetch) cache->access(addr, bytes, false);
+ if (type == LOAD || type == STORE) cache->access(addr, bytes, type == STORE);
}
};