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[riscv-isa-sim.git] / riscv / debug_module.cc

diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index de54a8377256346b8223c5a5fe6b4025b8400bfc..96de3c8ab234f59aa23cf079a16a9395f37acee4 100644 (file)
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -4,6 +4,7 @@
 #include "debug_defines.h"
 #include "opcodes.h"
 #include "mmu.h"
+#include "sim.h"
 
 #include "debug_rom/debug_rom.h"
 #include "debug_rom_defines.h"
@@ -16,12 +17,15 @@
 
 ///////////////////////// debug_module_t
 
-debug_module_t::debug_module_t(sim_t *sim, unsigned progbufsize, unsigned max_bus_master_bits) :
+debug_module_t::debug_module_t(sim_t *sim, unsigned progbufsize, unsigned max_bus_master_bits,
+    bool require_authentication) :
   progbufsize(progbufsize),
   program_buffer_bytes(4 + 4*progbufsize),
   max_bus_master_bits(max_bus_master_bits),
+  require_authentication(require_authentication),
   debug_progbuf_start(debug_data_start - program_buffer_bytes),
   debug_abstract_start(debug_progbuf_start - debug_abstract_size*4),
+  custom_base(0),
   sim(sim)
 {
   D(fprintf(stderr, "debug_data_start=0x%x\n", debug_data_start));
@@ -33,6 +37,7 @@ debug_module_t::debug_module_t(sim_t *sim, unsigned progbufsize, unsigned max_bu
   memset(halted, 0, sizeof(halted));
   memset(debug_rom_flags, 0, sizeof(debug_rom_flags));
   memset(resumeack, 0, sizeof(resumeack));
+  memset(havereset, 0, sizeof(havereset));
   memset(program_buffer, 0, program_buffer_bytes);
   program_buffer[4*progbufsize] = ebreak();
   program_buffer[4*progbufsize+1] = ebreak() >> 8;
@@ -65,7 +70,7 @@ void debug_module_t::reset()
 
   dmstatus = {0};
   dmstatus.impebreak = true;
-  dmstatus.authenticated = 1;
+  dmstatus.authenticated = !require_authentication;
   dmstatus.version = 2;
 
   abstractcs = {0};
@@ -87,6 +92,8 @@ void debug_module_t::reset()
     sbcs.access16 = true;
   if (max_bus_master_bits >= 8)
     sbcs.access8 = true;
+
+  challenge = random();
 }
 
 void debug_module_t::add_device(bus_t *bus) {
@@ -273,7 +280,7 @@ void debug_module_t::sb_read()
     } else if (sbcs.sbaccess == 2 && max_bus_master_bits >= 32) {
       sbdata[0] = sim->debug_mmu->load_uint32(address);
     } else if (sbcs.sbaccess == 3 && max_bus_master_bits >= 64) {
-      uint64_t value = sim->debug_mmu->load_uint32(address);
+      uint64_t value = sim->debug_mmu->load_uint64(address);
       sbdata[0] = value;
       sbdata[1] = value >> 32;
     } else {
@@ -342,8 +349,9 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value)
 
           result = set_field(result, DMI_DMCONTROL_HALTREQ, dmcontrol.haltreq);
           result = set_field(result, DMI_DMCONTROL_RESUMEREQ, dmcontrol.resumereq);
-          result = set_field(result, ((1L<<hartsellen)-1) <<
-              DMI_DMCONTROL_HARTSEL_OFFSET, dmcontrol.hartsel);
+          result = set_field(result, DMI_DMCONTROL_HARTSELHI,
+              dmcontrol.hartsel >> DMI_DMCONTROL_HARTSELLO_LENGTH);
+          result = set_field(result, DMI_DMCONTROL_HARTSELLO, dmcontrol.hartsel);
           result = set_field(result, DMI_DMCONTROL_HARTRESET, dmcontrol.hartreset);
          result = set_field(result, DMI_DMCONTROL_NDMRESET, dmcontrol.ndmreset);
           result = set_field(result, DMI_DMCONTROL_DMACTIVE, dmcontrol.dmactive);
@@ -383,6 +391,10 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value)
 
           result = set_field(result, DMI_DMSTATUS_IMPEBREAK,
               dmstatus.impebreak);
+          result = set_field(result, DMI_DMSTATUS_ALLHAVERESET,
+              havereset[dmcontrol.hartsel]);
+          result = set_field(result, DMI_DMSTATUS_ANYHAVERESET,
+              havereset[dmcontrol.hartsel]);
          result = set_field(result, DMI_DMSTATUS_ALLNONEXISTENT, dmstatus.allnonexistant);
          result = set_field(result, DMI_DMSTATUS_ALLUNAVAIL, dmstatus.allunavail);
          result = set_field(result, DMI_DMSTATUS_ALLRUNNING, dmstatus.allrunning);
@@ -462,6 +474,9 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value)
       case DMI_SBDATA3:
         result = sbdata[3];
         break;
+      case DMI_AUTHDATA:
+        result = challenge;
+        break;
       default:
         result = 0;
         D(fprintf(stderr, "Unexpected. Returning Error."));
@@ -585,6 +600,20 @@ bool debug_module_t::perform_abstract_command()
           }
         }
 
+      } else if (regno >= 0xc000 && (regno & 1) == 1) {
+        // Support odd-numbered custom registers, to allow for debugger testing.
+        unsigned custom_number = regno - 0xc000;
+        abstractcs.cmderr = CMDERR_NONE;
+        if (write) {
+          // Writing V to custom register N will cause future reads of N to
+          // return V, reads of N-1 will return V-1, etc.
+          custom_base = read32(dmdata, 0) - custom_number;
+        } else {
+          write32(dmdata, 0, custom_number + custom_base);
+          write32(dmdata, 1, 0);
+        }
+        return true;
+
       } else {
         abstractcs.cmderr = CMDERR_NOTSUP;
         return true;
@@ -611,6 +640,11 @@ bool debug_module_t::perform_abstract_command()
 bool debug_module_t::dmi_write(unsigned address, uint32_t value)
 {
   D(fprintf(stderr, "dmi_write(0x%x, 0x%x)\n", address, value));
+
+  if (!dmstatus.authenticated && address != DMI_AUTHDATA &&
+      address != DMI_DMCONTROL)
+    return false;
+
   if (address >= DMI_DATA0 && address < DMI_DATA0 + abstractcs.datacount) {
     unsigned i = address - DMI_DATA0;
     if (!abstractcs.busy)
@@ -643,13 +677,20 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value)
           if (!dmcontrol.dmactive && get_field(value, DMI_DMCONTROL_DMACTIVE))
             reset();
           dmcontrol.dmactive = get_field(value, DMI_DMCONTROL_DMACTIVE);
+          if (!dmstatus.authenticated)
+            return true;
           if (dmcontrol.dmactive) {
             dmcontrol.haltreq = get_field(value, DMI_DMCONTROL_HALTREQ);
             dmcontrol.resumereq = get_field(value, DMI_DMCONTROL_RESUMEREQ);
             dmcontrol.hartreset = get_field(value, DMI_DMCONTROL_HARTRESET);
             dmcontrol.ndmreset = get_field(value, DMI_DMCONTROL_NDMRESET);
-            dmcontrol.hartsel = get_field(value, ((1L<<hartsellen)-1) <<
-                DMI_DMCONTROL_HARTSEL_OFFSET);
+            dmcontrol.hartsel = get_field(value, DMI_DMCONTROL_HARTSELHI) <<
+              DMI_DMCONTROL_HARTSELLO_LENGTH;
+            dmcontrol.hartsel |= get_field(value, DMI_DMCONTROL_HARTSELLO);
+            dmcontrol.hartsel &= (1L<<hartsellen) - 1;
+            if (get_field(value, DMI_DMCONTROL_ACKHAVERESET)) {
+              havereset[dmcontrol.hartsel] = false;
+            }
           }
           processor_t *proc = current_proc();
           if (proc) {
@@ -725,7 +766,25 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value)
       case DMI_SBDATA3:
         sbdata[3] = value;
         return true;
+      case DMI_AUTHDATA:
+        D(fprintf(stderr, "debug authentication: got 0x%x; 0x%x unlocks\n", value,
+            challenge + secret));
+        if (require_authentication) {
+          if (value == challenge + secret) {
+            dmstatus.authenticated = true;
+          } else {
+            dmstatus.authenticated = false;
+            challenge = random();
+          }
+        }
+        return true;
     }
   }
   return false;
 }
+
+void debug_module_t::proc_reset(unsigned id)
+{
+  havereset[id] = true;
+  halted[id] = false;
+}