Update README

[riscv-isa-sim.git] / riscv / debug_module.h

diff --git a/riscv/debug_module.h b/riscv/debug_module.h
index 50107fcf562e520dc0da3d4664bd7736d9e76b23..5b43ed628c52b5cb4745b9872cdebbb91885c318 100644 (file)
--- a/riscv/debug_module.h
+++ b/riscv/debug_module.h
@@ -115,7 +115,12 @@ class debug_module_t : public abstract_device_t
 
     static const unsigned debug_abstract_size = 5;
     unsigned debug_abstract_start;
+    // R/W this through custom registers, to allow debuggers to test that
+    // functionality.
+    unsigned custom_base;
 
+    // We only support 1024 harts currently. More requires at least resizing
+    // the arrays below, and their corresponding special memory regions.
     static const unsigned hartsellen = 10;
 
     sim_t *sim;