Remove more vector stuff

[riscv-isa-sim.git] / riscv / decode.h

diff --git a/riscv/decode.h b/riscv/decode.h
index 7c99581a4e3b039922be57d9bb0b9f984759472f..1dfec6eeee6ef68e4eb0d9b528d38e0425dac75f 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -166,10 +166,6 @@ private:
   T data[N];
 };
 
-#define throw_illegal_instruction \
-  ({ if (utmode) throw trap_vector_illegal_instruction; \
-     else throw trap_illegal_instruction; })
-
 // helpful macros, etc
 #define RS1 XPR[insn.rtype.rs1]
 #define RS2 XPR[insn.rtype.rs2]
@@ -191,27 +187,19 @@ private:
 #define BTYPE_EADDR sext_xprlen(RS1 + BIMM)
 #define RM ({ int rm = insn.ftype.rm; \
               if(rm == 7) rm = (fsr & FSR_RD) >> FSR_RD_SHIFT; \
-              if(rm > 4) throw_illegal_instruction; \
+              if(rm > 4) throw trap_illegal_instruction; \
               rm; })
 
 #define xpr64 (xprlen == 64)
 
 #define require_supervisor if(unlikely(!(sr & SR_S))) throw trap_privileged_instruction
-#define require_xpr64 if(unlikely(!xpr64)) throw_illegal_instruction
-#define require_xpr32 if(unlikely(xpr64)) throw_illegal_instruction
+#define require_xpr64 if(unlikely(!xpr64)) throw trap_illegal_instruction
+#define require_xpr32 if(unlikely(xpr64)) throw trap_illegal_instruction
 #ifndef RISCV_ENABLE_FPU
 # define require_fp throw trap_illegal_instruction
 #else
 # define require_fp if(unlikely(!(sr & SR_EF))) throw trap_fp_disabled
 #endif
-#ifndef RISCV_ENABLE_VEC
-# define require_vector throw trap_illegal_instruction
-#else
-# define require_vector \
-  ({ if(!(sr & SR_EV)) throw trap_vector_disabled; \
-    else if (!utmode && (vecbanks_count < 3)) throw trap_vector_bank; \
-  })
-#endif
 
 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
 #define set_fp_exceptions ({ set_fsr(fsr | \
@@ -235,49 +223,4 @@ private:
        npc = (x); \
      } while(0)
 
-// vector stuff
-#define VL vl
-
-#define UT_RS1(idx) uts[idx]->XPR[insn.rtype.rs1]
-#define UT_RS2(idx) uts[idx]->XPR[insn.rtype.rs2]
-#define UT_RD(idx) uts[idx]->XPR.write_port(insn.rtype.rd)
-#define UT_RA(idx) uts[idx]->XPR.write_port(1)
-#define UT_FRS1(idx) uts[idx]->FPR[insn.ftype.rs1]
-#define UT_FRS2(idx) uts[idx]->FPR[insn.ftype.rs2]
-#define UT_FRS3(idx) uts[idx]->FPR[insn.ftype.rs3]
-#define UT_FRD(idx) uts[idx]->FPR.write_port(insn.ftype.rd)
-#define UT_RM(idx) ((insn.ftype.rm != 7) ? insn.ftype.rm : \
-              ((uts[idx]->fsr & FSR_RD) >> FSR_RD_SHIFT))
-
-#define UT_LOOP_START for (int i=0;i<VL; i++) {
-#define UT_LOOP_END }
-#define UT_LOOP_RS1 UT_RS1(i)
-#define UT_LOOP_RS2 UT_RS2(i)
-#define UT_LOOP_RD UT_RD(i)
-#define UT_LOOP_RA UT_RA(i)
-#define UT_LOOP_FRS1 UT_FRS1(i)
-#define UT_LOOP_FRS2 UT_FRS2(i)
-#define UT_LOOP_FRS3 UT_FRS3(i)
-#define UT_LOOP_FRD UT_FRD(i)
-#define UT_LOOP_RM UT_RM(i)
-
-#define VEC_LOAD(dst, func, inc) \
-  reg_t addr = RS1; \
-  UT_LOOP_START \
-    UT_LOOP_##dst = mmu.func(addr); \
-    addr += inc; \
-  UT_LOOP_END
-
-#define VEC_STORE(src, func, inc) \
-  reg_t addr = RS1; \
-  UT_LOOP_START \
-    mmu.func(addr, UT_LOOP_##src); \
-    addr += inc; \
-  UT_LOOP_END
-
-enum vt_command_t
-{
-  vt_command_stop,
-};
-
 #endif