Update README

[riscv-isa-sim.git] / riscv / execute.cc

diff --git a/riscv/execute.cc b/riscv/execute.cc
index b302daac78b8f29b83df6945314c9f665ecc588e..e639e90462cf9063404f5cfde99b712ad201b94f 100644 (file)
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -76,7 +76,7 @@ static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
 {
   commit_log_stash_privilege(p);
   reg_t npc = fetch.func(p, fetch.insn, pc);
-  if (!invalid_pc(npc)) {
+  if (npc != PC_SERIALIZE_BEFORE) {
     commit_log_print_insn(p->get_state(), pc, fetch.insn);
     p->update_histogram(pc);
   }
@@ -109,11 +109,11 @@ void processor_t::step(size_t n)
      if (unlikely(invalid_pc(pc))) { \
        switch (pc) { \
          case PC_SERIALIZE_BEFORE: state.serialized = true; break; \
-         case PC_SERIALIZE_AFTER: n = ++instret; break; \
+         case PC_SERIALIZE_AFTER: ++instret; break; \
+         case PC_SERIALIZE_WFI: n = ++instret; break; \
          default: abort(); \
        } \
        pc = state.pc; \
-       check_pc_alignment(pc); \
        break; \
      } else { \
        state.pc = pc; \
@@ -130,9 +130,11 @@ void processor_t::step(size_t n)
         {
           if (unlikely(!state.serialized && state.single_step == state.STEP_STEPPED)) {
             state.single_step = state.STEP_NONE;
-            enter_debug_mode(DCSR_CAUSE_STEP);
-            // enter_debug_mode changed state.pc, so we can't just continue.
-            break;
+            if (state.dcsr.cause == DCSR_CAUSE_NONE) {
+              enter_debug_mode(DCSR_CAUSE_STEP);
+              // enter_debug_mode changed state.pc, so we can't just continue.
+              break;
+            }
           }
 
           if (unlikely(state.single_step == state.STEP_STEPPING)) {