[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / add.h

diff --git a/riscv/insns/add.h b/riscv/insns/add.h
index 746cd80678ca0b19b35cd2bb48c69feb2d1a65d9..f7dede9f3de53530cf896ff7a103a97d513ad16e 100644 (file)
--- a/riscv/insns/add.h
+++ b/riscv/insns/add.h
@@ -1,2 +1,2 @@
 require64;
-RC = RA + RB;
+RDR = RS1 + RS2;