[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / amo_max.h

diff --git a/riscv/insns/amo_max.h b/riscv/insns/amo_max.h
index 6e3eeb66db9fe6c40e76185c281216d5757e6069..296b86a620ffcb4383deaf9900100ae7159673ce 100644 (file)
--- a/riscv/insns/amo_max.h
+++ b/riscv/insns/amo_max.h
@@ -1,4 +1,4 @@
 require64;
-sreg_t v = mmu.load_int64(RB);
-mmu.store_uint64(RB, std::max(sreg_t(RA),v));
-RC = v;
+sreg_t v = mmu.load_int64(RS1);
+mmu.store_uint64(RS1, std::max(sreg_t(RS2),v));
+RDR = v;