[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / andi.h

diff --git a/riscv/insns/andi.h b/riscv/insns/andi.h
index 86a045c2ff0b54da48954d0a415f41b17237fb76..ada6657d65e05b62f7576c1f3ccd2be012246ef9 100644 (file)
--- a/riscv/insns/andi.h
+++ b/riscv/insns/andi.h
@@ -1 +1 @@
-RA = IMM & RB;
+RDI = IMM & RS1;