[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / c_eq_s.h

diff --git a/riscv/insns/c_eq_s.h b/riscv/insns/c_eq_s.h
index 5500c4cdadc09d4b0b1c0f580b8563b4636140b1..0a2ccd916ff57672097565f62d3a54ed8a1e316c 100644 (file)
--- a/riscv/insns/c_eq_s.h
+++ b/riscv/insns/c_eq_s.h
@@ -1,3 +1,3 @@
 require_fp;
-RC = f32_eq(FRA, FRB);
+RDR = f32_eq(FRS1, FRS2);
 set_fp_exceptions;