work towards rvc 1.8

[riscv-isa-sim.git] / riscv / insns / c_flw.h

diff --git a/riscv/insns/c_flw.h b/riscv/insns/c_flw.h
index ad737aa015ddf1b740dd210d159c3fb0ddbad676..0be27a94a4cc1d16cba37f9ac34cd38ddf258437 100644 (file)
--- a/riscv/insns/c_flw.h
+++ b/riscv/insns/c_flw.h
@@ -3,6 +3,6 @@ if (xlen == 32) {
   require_extension('F');
   require_fp;
   WRITE_RVC_FRS2S(MMU.load_int32(RVC_RS1S + insn.rvc_lw_imm()));
-} else {
+} else { // c.ld
   WRITE_RVC_RS2S(MMU.load_int64(RVC_RS1S + insn.rvc_ld_imm()));
 }