Implement Q extension

[riscv-isa-sim.git] / riscv / insns / c_fsw.h

diff --git a/riscv/insns/c_fsw.h b/riscv/insns/c_fsw.h
index b924a4689dc58dc4b0e7352c135d5eecefbac6d2..70858229652189553e792b82a5a2178570107145 100644 (file)
--- a/riscv/insns/c_fsw.h
+++ b/riscv/insns/c_fsw.h
@@ -2,7 +2,7 @@ require_extension('C');
 if (xlen == 32) {
   require_extension('F');
   require_fp;
-  MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S.v);
+  MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S.v[0]);
 } else { // c.sd
   MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S);
 }