work towards rvc 1.8

[riscv-isa-sim.git] / riscv / insns / c_fswsp.h

diff --git a/riscv/insns/c_fswsp.h b/riscv/insns/c_fswsp.h
index 8e2fedcd1a18dc1d5e23b021f941f3bd043577f1..c13aa12f8908c1819402319dc5c09e416420d7cf 100644 (file)
--- a/riscv/insns/c_fswsp.h
+++ b/riscv/insns/c_fswsp.h
@@ -3,6 +3,6 @@ if (xlen == 32) {
   require_extension('F');
   require_fp;
   MMU.store_uint32(RVC_SP + insn.rvc_swsp_imm(), RVC_FRS2);
-} else {
+} else { // c.sdsp
   MMU.store_uint64(RVC_SP + insn.rvc_sdsp_imm(), RVC_RS2);
 }