Implement Q extension

[riscv-isa-sim.git] / riscv / insns / c_fswsp.h

diff --git a/riscv/insns/c_fswsp.h b/riscv/insns/c_fswsp.h
index 011de555f3de08cb426f41e01b8c65931b2eca44..c5a003fcd1f057df93f407747173772f3ab7a4df 100644 (file)
--- a/riscv/insns/c_fswsp.h
+++ b/riscv/insns/c_fswsp.h
@@ -2,7 +2,7 @@ require_extension('C');
 if (xlen == 32) {
   require_extension('F');
   require_fp;
-  MMU.store_uint32(RVC_SP + insn.rvc_swsp_imm(), RVC_FRS2.v);
+  MMU.store_uint32(RVC_SP + insn.rvc_swsp_imm(), RVC_FRS2.v[0]);
 } else { // c.sdsp
   MMU.store_uint64(RVC_SP + insn.rvc_sdsp_imm(), RVC_RS2);
 }