[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / c_le_s.h

diff --git a/riscv/insns/c_le_s.h b/riscv/insns/c_le_s.h
index e6e26b3d944d904db6ca6fe258df626a323ec941..7350a9e066111509d7d050fffde08754bd9962ab 100644 (file)
--- a/riscv/insns/c_le_s.h
+++ b/riscv/insns/c_le_s.h
@@ -1,3 +1,3 @@
 require_fp;
-RC = f32_le(FRA, FRB);
+RDR = f32_le(FRS1, FRS2);
 set_fp_exceptions;