New RV64C proposal

[riscv-isa-sim.git] / riscv / insns / c_li.h

diff --git a/riscv/insns/c_li.h b/riscv/insns/c_li.h
index 06d7bf2ae286f96b542a9401cc5d309d105221d5..52e99c96005b996b87bce4b9552cb936bca69c6a 100644 (file)
--- a/riscv/insns/c_li.h
+++ b/riscv/insns/c_li.h
@@ -1,7 +1,7 @@
 require_extension('C');
-if (insn.rvc_rd() == 0) {
-  if (insn.rvc_imm() == -32) // c.sbreak
-    throw trap_breakpoint();
-  throw trap_illegal_instruction();
-} else // c.li
+require(insn.rvc_rd() != 0);
+if (insn.rvc_imm() == 0) { // c.jr
+  set_pc(RVC_RS1 & ~reg_t(1));
+} else {
   WRITE_RD(insn.rvc_imm());
+}