[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / div.h

diff --git a/riscv/insns/div.h b/riscv/insns/div.h
index f0c2d2be5742a9ec67ee1384adc0383bf203e6a3..2d6edfca0e144956e88542384aea55dba8fd29d3 100644 (file)
--- a/riscv/insns/div.h
+++ b/riscv/insns/div.h
@@ -1,2 +1,2 @@
 require64;
-RC = sreg_t(RA) / sreg_t(RB);
+RDR = sreg_t(RS1) / sreg_t(RS2);