[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / divu.h

diff --git a/riscv/insns/divu.h b/riscv/insns/divu.h
index a4e3f4f27355d4ad4434a3a29114af762bc04618..35eee14eae11774afdcbb4d27c49d2c51b6994e0 100644 (file)
--- a/riscv/insns/divu.h
+++ b/riscv/insns/divu.h
@@ -1,2 +1,2 @@
 require64;
-RC = RA / RB;
+RDR = RS1 / RS2;